_list -1 ;__________________________________________________________________________ ; ; FILE : Aliases_88.inc ; DATE : 26/05/06 ; LAST UPDATE : 25/12/06 ; ; DESCRIPTION : Some useful aliases for 16F88. ; !!! case sensitive !!! ; ; AUTHOR : FD ;__________________________________________________________________________ ; ; HISTORY ;__________________________________________________________________________ ; 24/06/06 Add PIR1 bits ; 25/12/06 Add TMR1 registers ;__________________________________________________________________________ ; ; MISC. ;__________________________________________________________________________ INT = 4 ; Interrupt vector address RESET = 0 ; Reset vector address YES = 1 NO = 0 #define Hz #define kHz * 1000 #define MHz * 1000000 ;__________________________________________________________________________ ; ; REGISTER & BIT DEFINITIONS ;__________________________________________________________________________ ;----- TIMER0 REGISTER ---------------------------------------------------- #define Timer0 TMR0 ;----- PC REGISTERS ------------------------------------------------------- #define PcLow PCL ; PC least significant byte #define PcHigh PCLATH ; Write buffer for the upper 5 bits of PC ;----- STATUS REGISTER ---------------------------------------------------- #define Status STATUS ;----- STATUS Bits ; Register Bank Select bit for indirect addressing #define FlagIndRegPage Status, IRP ; R/W-0 ; Register Bank Select bits for direct addressing #define FlagRegPage1 Status, RP1 ; R/W-0 #define FlagRegPage0 Status, RP0 ; R/W-0 #define Flag_TimeOut Status, NOT_TO ; R -1 #define Flag_PowerDown Status, NOT_PD ; R -1 #define FlagZero Status, Z ; R/W-x #define FlagDigitCarry Status, DC ; R/W-x #define FlagCarry Status, C ; R/W-x ;----- INDF & FSR REGISTERS ----------------------------------------------- #define Indirect INDF #define Pointer FSR ;----- PORTS -------------------------------------------------------------- #define PortA PORTA #define TrisA TRISA #define PortB PORTB #define TrisB TRISB ;----- INTCON REGISTER ---------------------------------------------------- #define InterruptControlRegister INTCON ;----- INTCON Bits #define FlagGlobalInterruptEnable InterruptControlRegister,GIE ; R/W-0 ; #define FlagEEWrInterruptEnable InterruptControlRegister,PEIE ; R/W-0 #define FlagTimer0InterruptEnable InterruptControlRegister,TMR0IE ; R/W-0 #define FlagRB0InterruptEnable InterruptControlRegister,INTE ; R/W-0 #define FlagPortBInterruptEnable InterruptControlRegister,RBIE ; R/W-0 #define FlagInterruptOnTmr0 InterruptControlRegister,TMR0IF ; R/W-0 #define FlagInterruptOnRB0 InterruptControlRegister,INTF ; R/W-0 #define FlagInterruptOnPortB InterruptControlRegister,RBIF ; R/W-x ;----- PIR1 REGISTER ------------------------------------------------------ #define PeripheralInterruptFlags PIR1 ;----- PIR1 Bits #define FlagCCP_Interrupt PeripheralInterruptFlags,CCP1IF #define FlagTimer1_Overflow PeripheralInterruptFlags,TMR1IF #define FlagReceiveInterrupt PeripheralInterruptFlags,RCIF #define FlagTransmitInterrupt PeripheralInterruptFlags,TXIF ;----- TMR1 REGISTERS ----------------------------------------------------- #define Timer1 TMR1L #define Timer1_ControlRegister T1CON ;----- T1CON Bits ; to do... ;----- TMR2 REGISTERS ----------------------------------------------------- ; #define Timer2_ControlRegister T2CON ; #define Timer2_PeriodRegister PR2 ;----- T2CON Bits ; to do... ;----- CCP REGISTERS ------------------------------------------------------ ; #define CCP_Register CCPR1L ; #define CCP_ControlRegister CCP1CON ;----- CCP1CON Bits ; #define DutyCycleBit0 CCP1Y CCP1CON ; #define DutyCycleBit1 CCP1X CCP1CON ;----- USART REGISTERs ---------------------------------------------------- #define SerialBaudRateRegister SPBRG ; Bank_1 #define ReceiveStatusRegister RCSTA ; Bank_0 #define ReceiveRegister RCREG ; Bank_0 #define TransmitStatusRegister TXSTA ; Bank_1 #define TransmitRegister TXREG ; Bank_0 ;----- RCSTA Bits #define SerialPortEnable ReceiveStatusRegister, SPEN ; R/W-0 #define _9BitReceiveEnable ReceiveStatusRegister, RX9 ; R/W-0 #define SingleReceiveEnable ReceiveStatusRegister, SREN ; R/W-0 #define ContinuousReceiveEnable ReceiveStatusRegister, CREN ; R/W-0 ; #define AddressDetectEnable ReceiveStatusRegister, ADEN ; R/W-0 #define FramingError ReceiveStatusRegister, FERR ; R -0 #define OverrunError ReceiveStatusRegister, OERR ; R -0 #define _9thBitOfReceivedData ReceiveStatusRegister, RX9D ; R -x ;----- TXSTA Bits #define ClockSourceSelect TransmitStatusRegister, CSRC ; R/W-0 #define _9BitTransmitEnable TransmitStatusRegister, TX9 ; R/W-0 #define TransmitEnable TransmitStatusRegister, TXEN ; R/W-0 #define USART_ModeSelect TransmitStatusRegister, SYNC ; R/W-0 ; #define HighBaudRateSelect TransmitStatusRegister, BRGH ; R/W-0 #define TransmitShiftRegisterStatus TransmitStatusRegister, TRMT ; R -1 #define _9thBitOfTransmitData TransmitStatusRegister, TX9D ; R/W-0 ;----- COMPARATOR REGISTER ------------------------------------------------ #define ComparatorModule CMCON COMPARATORS_OFF = 7 ;----- CMCON Bits ; to do... ;----- VRCON Bits ; to do... ;----- OPTION_REG REGISTER ------------------------------------------------ #define OptionReg OPTION_REG ;----- OPTION Bits #define FlagPullUpDisable OptionReg,NOT_RBPU ; R/W-1 #define FlagInterruptEdgeSelect OptionReg,INTEDG ; R/W-1 #define FlagTimer0ClockSelect OptionReg,T0CS ; R/W-1 #define FlagTimer0EdgeSelect OptionReg,T0SE ; R/W-1 #define FlagPrescalerAssignment OptionReg,PSA ; R/W-1 #define FlagPrescalerRateSelect2 OptionReg,PS2 ; R/W-1 #define FlagPrescalerRateSelect1 OptionReg,PS1 ; R/W-1 #define FlagPrescalerRateSelect0 OptionReg,PS0 ; R/W-1 ;----- PIE1 REGISTER ------------------------------------------------------ #define PeripheralInterruptEnable PIE1 ;----- PIE1 Bits ; to do... ;----- PCON REGISTER ------------------------------------------------------ ;----- PCON Bits ; to do... ;----- EEPROM REGISTERS --------------------------------------------------- #define EE_Data EEDATA #define EE_Adr EEADR #define EE_Con1 EECON1 #define EE_Con2 EECON2 ;----- EECON1 Bits ; #define FlagEE_Error EE_Con1,WRERR ; R/W-x ; #define FlagEE_WriteEnable EE_Con1,WREN ; R/W-0 ; #define FlagWriteControl EE_Con1,WR ; R/S-0 ; #define FlagReadControl EE_Con1,RD ; R/S-x ;-------------------------------------------------------------------------- BANK_0_BEGIN = 0x20 BANK_0_END = 0x6F BANK_1_BEGIN = 0xA0 BANK_1_END = 0xEF BANK_2_BEGIN = 0x110 BANK_2_END = 0x16F BANK_3_BEGIN = 0x190 BANK_3_END = 0x1EF COMMON_BEGIN = 0x70 COMMON_END = 0x7F ;-------------------------------------------------------------------------- _list +1