;========================================================================================== ; PIC16F628A Fast Huff Puff VFO Stabiliser ; ; (c) Cumbria Designs ; ; This software is provided free of charge for non commercial use. The software is provided ; without warranty or licence and no liability is accepted by the author or Cumbria Designs ; for any loss, injury, mishap, inconvenience or misdemeanor arising from the use of the ; software in whole or part. In using this software and the code compiled from it, you agree ; to these terms. ; ; We ask that in return for downloading and/or using this software in any way, you make a ; donation to a deserving charity of your choice. How much is up to you. ; ; Ron Taylor, Cumbria Designs ; ;========================================================================================== ; ; Revision History ; ; December 2006 Version 1.0 ; ; ;========================================================================================== ; ; Pin Out ; ; VFO Input PORTB,6 ; ; Output PORTB,4 ; ;========================================================================================== list p=16F628A ; list directive to define processor #include ; processor specific variable definitions ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'03FF' _CP_75 EQU H'17FF' _CP_50 EQU H'2BFF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _ER_OSC_CLKOUT EQU H'3FFF' _ER_OSC_NOCLKOUT EQU H'3FFE' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _EXTCLK_OSC EQU H'3FEF' _LP_OSC EQU H'3FEC' _XT_OSC EQU H'3FED' _HS_OSC EQU H'3FEE' __config (_CP_OFF & _PWRTE_ON & _WDT_OFF & _LVP_OFF & _HS_OSC & _MCLRE_OFF); Equates ;========================================================================================== ; Port Definitions ; ; ;========================================================================================== ; PORTB control_out EQU 0x04 ; Control output to integrator ;========================================================================================== ; ; File Register Definitions ; ; ;========================================================================================== CBLOCK 0x20 ; Start of Register Memory ; temp ; Used in detect routine delay ; Delay counter SR8 ; 504 Bit Shift Register SR16 ; SR24 ; Digit in register name represents higher order bit number of register SR32 ; Registers must occupy consective memory addresses for the "shift through SR40 ; carry bit" action to function SR48 SR56 SR64 SR72 SR80 SR88 SR96 SR104 SR112 SR120 SR128 SR136 SR144 SR152 SR160 SR168 SR176 SR184 SR192 SR200 SR208 SR216 SR224 SR232 SR240 SR248 SR256 SR264 SR272 SR280 SR288 SR296 SR304 SR312 SR320 SR328 SR336 SR344 SR352 SR360 SR368 SR376 SR384 SR392 SR400 SR408 SR416 SR424 SR432 SR440 SR448 SR456 SR464 SR472 SR480 SR488 SR496 SR504 ENDC CBLOCK 0xA0 ; SR512 SR520 SR528 SR536 SR544 SR552 SR560 SR568 SR576 SR584 SR592 SR600 SR608 SR616 SR624 SR632 SR640 SR648 SR656 SR664 SR672 SR680 SR688 SR696 SR704 SR712 SR720 SR728 SR736 SR744 SR752 SR760 SR768 SR776 SR784 SR792 SR800 SR808 SR816 SR824 SR832 SR840 SR848 SR856 SR864 SR872 SR880 SR888 SR896 SR904 SR912 SR920 SR928 SR936 SR944 SR952 SR960 SR968 SR976 SR984 SR992 SR1000 ; ENDC ;========================================================================================== ; ; MACRO AREA ; ;========================================================================================== ; Bank Select Macros to simplify bank changes Bank0 MACRO bcf STATUS,RP0 ; Select Bank 0 bcf STATUS,RP1 ; ENDM Bank1 MACRO bsf STATUS,RP0 ; Select Bank 1 bcf STATUS,RP1 ; ENDM Bank2 MACRO bcf STATUS,RP0 ; Select Bank 2 bsf STATUS,RP1 ; ENDM Bank3 MACRO bsf STATUS,RP0 ; Select Bank 3 bsf STATUS,RP1 ; ENDM ;================================================================================================ ; ; Start of Program ; ;================================================================================================ Start ; Initialise ports, modules and variables Bank0 clrf INTCON ; No interrupts for now movlw 0x07 ; Turn OFF Comparators movwf CMCON banksel OPTION_REG bcf OPTION_REG,7; No weak pull ups movlw b'11101111' ; PORT B bit 4 set to output, 6 set to input for VFO banksel TRISB movwf TRISB banksel T1CON ; movlw b'00000111' ; Set TMR1ON, TMR1CS and T1SYNC movwf T1CON ; Timer 1 ON, External Clock, Async Operation, Prescale=1 ;================================================================================================ ; ; Main ; ; Cyclic loop from which all routines are called. Instruction times are given in machines cycles. ; These are used to form the overall cycle and hence sampling time. ; ;================================================================================================ Main ; bsf SR8,0 ; 1 Set input to shift register btfss TMR1L,0 ; 2 Test least significant byte of running count bcf SR8,0 ; 3 Input sample was zero, clear shift register input bit call Detect ; 23 (2+18) call Shift ; 157(2+131) call Sample_Delay ;159+T (2+T) goto Main ; 161+T Back round again ; The Shift and Detect routines sit inside the main gate timing loop, hence ; their run times contribute to the gate duration Shift ; Move shift register contents left one bit through carry flag ; 504 Bit Shift Register bcf STATUS,C ; Clear Carry bit to prevent any carry in rlf SR8,f ; 1 Machine cycles rlf SR16,f ; 2 rlf SR24,f ; 3 rlf SR32,f ; 4 rlf SR40,f ; 5 rlf SR48,f ; 6 rlf SR56,f ; 7 rlf SR64,f ; 8 rlf SR72,f ; 9 rlf SR80,f ; 10 rlf SR88,f rlf SR96,f rlf SR104,f rlf SR112,f rlf SR120,f rlf SR128,f rlf SR136,f rlf SR144,f rlf SR152,f rlf SR160,f rlf SR168,f rlf SR176,f rlf SR184,f rlf SR192,f rlf SR200,f rlf SR208,f rlf SR216,f rlf SR224,f rlf SR232,f rlf SR240,f rlf SR248,f rlf SR256,f rlf SR264,f rlf SR272,f rlf SR280,f rlf SR288,f rlf SR296,f rlf SR304,f rlf SR312,f rlf SR320,f rlf SR328,f rlf SR336,f rlf SR344,f rlf SR352,f rlf SR360,f rlf SR368,f rlf SR376,f rlf SR384,f rlf SR392,f rlf SR400,f rlf SR408,f rlf SR416,f rlf SR424,f rlf SR432,f rlf SR440,f rlf SR448,f rlf SR456,f rlf SR464,f rlf SR472,f rlf SR480,f ; 60 rlf SR488,f ; 61 rlf SR496,f ; 62 rlf SR504,f ; 63 Bank1 ; 65 Switch to next set of registers in Bank1 ; btfsc STATUS,C ; bsf SR512,0 rlf SR512,f ; 66 rlf SR520,f rlf SR528,f rlf SR536,f rlf SR544,f rlf SR552,f rlf SR560,f rlf SR568,f rlf SR576,f rlf SR584,f rlf SR592,f rlf SR600,f rlf SR608,f rlf SR616,f rlf SR624,f rlf SR632,f rlf SR640,f rlf SR648,f rlf SR656,f rlf SR664,f rlf SR672,f rlf SR680,f rlf SR688,f rlf SR696,f rlf SR704,f rlf SR712,f rlf SR720,f rlf SR728,f rlf SR736,f rlf SR744,f rlf SR752,f rlf SR760,f rlf SR768,f rlf SR776,f rlf SR784,f rlf SR792,f rlf SR800,f rlf SR808,f rlf SR816,f rlf SR824,f rlf SR832,f rlf SR840,f rlf SR848,f rlf SR856,f rlf SR864,f rlf SR872,f rlf SR880,f rlf SR888,f rlf SR896,f rlf SR904,f rlf SR912,f rlf SR920,f rlf SR928,f rlf SR936,f rlf SR944,f rlf SR952,f rlf SR960,f rlf SR968,f rlf SR976,f rlf SR984,f ;125 rlf SR992,f ;126 rlf SR1000,f ;127 Bank0 ;129 Back to Bank 0 return ;131 Back to calling routine Detect ; Generate Correction Signal movf SR8,w ; 1 Get input to shift register andlw 0x01 ; 2 Mask tap 1 ,the shift register input movwf temp ; 3 Save result movlw 0x00 ; 4 Clear w Bank1 ; 6 btfsc SR1000,7 ; 7 Get bit state of tap 1000 of the shift register movlw 0x01 ; 8 Set w to 1 Bank0 ; 10 xorwf temp,f ; 11 XOR input and output and save result in temp btfsc temp,0 ; 12 Test result goto Output_low ; 14 goto Output_high ; 15 Output_high bsf PORTB, control_out ; 16 Set output high return ; 18 Back to calling routine Output_low nop ; 15 Balancing nop bcf PORTB, control_out ; 16 Set output low return ; 18 Back to calling routine ;================================================================================================ ; ; Delay Routine ; ; The main process times are padded out with an additional delay to produce the required ; sampling rate and hence lock point spacing and correction signal refresh rate. The total ; cyclical process time is chosen such that the time taken for a bit to traverse the shift ; register produces a gate period that will give the required frequency resolution (lock ; point spacing). E.g. 100mSec = 10Hz ; ; For a 20MHz clock the machine cycle time is 200nSec, the sampling period is ; the sum of the process times (Ptot) plus the sample delay duration. Calculate the ; Sampling Delay period to pad out the process time for a given sampling rate ; as follows; ; ; For a 10kHz sampling rate the required clock period is 100uSec ; ; Clock period = Ptot + Delay ; Delay = Clock Rate - Ptot ; Delay = 100uSec - 161*200nSec ; Delay = 67800nSec ; Delay = 339 Machine Cycles ; ; ; ; Lock Point Spacing = 2fs/tap number ; ; Therefore, the additional delay to produce the required sampling rate is 409 machine cycles ; ;================================================================================================ ;Sample_Delay ; 910 machine cycle delay ; movlw 0x5A ; 1 Load Outer counter with 90d ; movwf delay ; 2 ;Delay1 ; nop ; 1 10 Machine Cycle loop ; nop ; 2 x90 = 900 + 2 from initialisation -1 from exit ; nop ; 3 = 901 ; nop ; 4 ; nop ; 5 ; nop ; 6 ; nop ; 7 ; decfsz delay,f ; 8 900 ; goto Delay1 ; 10 ; nop ; 902 ; nop ; 903 ; nop ; 904 ; nop ; 905 ; nop ; 906 ; nop ; 907 ; nop ; 908 Pad out with Machine cycles to make up to 910 ; return ; 910 Sample_Delay ; 339 machine cycle delay movlw 0x21 ; 1 Load Outer counter with 33d movwf delay ; 2 Delay1 nop ; 1 10 Machine Cycle loop nop ; 2 x33 = 330 + 2 from initialisation -1 from exit nop ; 3 = 331 nop ; 4 nop ; 5 nop ; 6 nop ; 7 decfsz delay,f ; 8 330 goto Delay1 ; 10 nop ; 332 Pad out with Machine cycles to make up to 190 nop ; 333 nop ; 334 nop ; 335 nop ; 336 nop ; 337 return ; 339 END