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The following downloads and designs are the copy right of Cumbria Designs and are provided free for non commercial use. In return for using any of the material provided below, we ask that you make a donation to a deserving charity. How much and to which charity is up to you of course. We hope that you find these downloads a useful addition to your projects.


A PIC Fast Huff Puff Stabiliser

C-1 Controller Source Code

DFT Tone Decoder in a 16F628

RAMU Remote Antenna Matching Unit

The Digi-Pot - A PIC12F683 behaves as a dual rate multi turn tuning pot

Digital AGC Published in SPRAT 144

A Simple GPS Disciplined Oscillator using the Jupiter Receiver 10kHz Reference

A PIC Fast Huff Puff Stabiliser


The software and circuit described in this article implements a "Fast Huff Puff" VFO stabiliser in a PIC processor. The design is much simpler in terms of circuit complexity when compared to the discrete Fast Huff Puff approach because many of the circuit functions are performed by software and hardware internal to the PIC device. The result is a very simple circuit with surprisingly good performance. Two variants are offered here, one for the more common PIC16F628A giving 20Hz lock points with a 10kHz sampling rate and an improved version for the PIC16F88 giving 10Hz lock points at a 10kHz sampling rate. Both designs use the same circuit, only the software differs.  


A simplified block diagram, of the PIC stabiliser is given below. The input signal is squared and passed to an asynchronous counter TMR1L, where it is sampled at 10kHz. The use of TMR1 provides a convenient method of sampling the input signal but introduces a divide by two action, effectively halving the potential lock point spacing. The sampling rate is much lower than the VFO frequency and the duration the sampling will span many cycles of VFO, importantly though the process is consistent in time and produces a 1 or a 0 depending upon the phase of the VFO at the instant the sampling gate shuts. The sampled signal is then branched into two paths, one goes direct to the phase detector, (a software XOR function), the other enters a delay line formed by a shift register, again clocked by the sampling clock. The shift register delay is the number of stages multiplied by the sampling clock period; T=Nts. The output of the shift register which carries the delayed samples, is passed to the other input of the XOR for comparison with the current sample. The output of the XOR is presented externally on PORTB,0 for averaging by the external integrator circuit before being applied to the VFO correction varactor. 

The XOR detector is a very simple but extremely effective phase detector. It action always produces a correction output irrespective if one is needed. Sometimes it is right, other times it is wrong, but when it is wrong the phase relationship at its inputs cause it to correct itself on the next “decision”. As Peter Lawton, G7IXH inventor of the Fast Huff Puff system described; "..over many samples the XOR will statistically always produce an output that will drive the VFO towards the nearest lock point." The resultant stability of the stabiliser is set by the processor clock, in this design a 20MHz crystal.

The lock point spacing is given by;  

Lock Point spacing (Hz) = 2fs/N   

Where fs is the sampling frequency and N is the number of shift register stages.

The 16F628 software uses 1000 step shift register defined in General Purpose Register memory (GPR) to produce 20Hz lock points with a 10kHz sampling rate. The 16F88 has a much larger GPR memory area and so can accommodate a larger shift register. In the design offered here a 2000 step shift register is used to give 10Hz lock point spacing at 10kHz sampling rate. The sampling rate is set by the program execution time. With a 20MHz clock and 2000 step shift register 10kHz is approaching the upper limit. Faster PICs or over clocking will produce higher sampling rates and a closer lock point spacing. Decade values for sampling rate and lock points have been chosen only for convenience of testing. By streamlining the program and using non decade values, a slight increase in sampling rates and reduction of lock point spacing will be possible. 

Whilst the designs have only been tested to 13MHz, current PIC performance should allow operation at input frequencies up to 50MHz. Higher input frequencies at VHF and UHF could also be accommodated by ether mixing down or dividing the oscillator source before applying it to the PIC input. If division is used this will increase the lock point spacing as a factor of the divisor value.

The circuit for the Fast Huff Puff stabiliser is given on the right. In some applications the addition of an operational amplifier integrator may be desirable to provide adjustment of the varactor tuning range. There is plenty of scope for future development with newer PIC families offering the potential for larger shift registers and lower lock point spacing at higher sampling rates. Peter Lawton has produced a simulator for computer modeling of Huff Puff systems which provides graphical information of performance. This is a very useful tool for aiding the development of Huff Puff schemes and is available for download at http://www.plvideo.com/personalpage1.html

Circuit Diagram (click to enlarge)


Two sets of files are provided for each PIC device. One in Assembler language format and a compiled hex file for loading into the PIC using any convenient programmer. the Assembler language programs can be read using a text editor such as notepad. To compile or modify these programs you will need to use Microchip's  MPLAB which is available as a free download on the Microchip website; www.microchip.com 

Future Developments

There are two clear program improvements that can easily be made. The first is to use an interrupt driven sampling routine to replace the carefully time cyclic program execution time. The second is to add a lock detector using perhaps the TMR1 count to detect when subsequent counts differ by 1 count or less. This could then drive a Lock LED on one of the spare port pins. 








New Versions!

It didn't take long! shortly after the RadCom TT article was published two new variants appeared. the first was from Francis Dupont F6HSI followed by a 16F84 version from Chas Fletcher noted for his "Stay Put" Huff Puff design in 2000/2001. 

Francis Dupont F6HSI, has been experimenting with the original assembler based software and has produced a new "asm" version for the 16F88 that makes extensive use of the MPASM Macro language. This new version is easier to configure and serves as an excellent tutorial in MPASM Macro programming. To be able to compile this version you will need to include the "inc" files in the "MPASM Suite" directory. Great piece of work and huge programming improvement over my "long hand" code. 

Francis has also re-worked the original hardware design to produce a very professional PCB version with a TXCO reference. 

Well done Francis!



F6HSI Version






Chas Fletcher adapted my 16F628 code for the 16F84 and in doing so uncovered a subtle difference in the internal operation of the two processors; "Having viewed your code and the F6HSI exercise in using MPLab assembler, I decided to have a go with the only PIC I had handy, a 16F84. This restricted the size of the SR as it has limited ram and as I have always been keen on interrupts, I put the sampling and shifting code in an ISR. Worked straight away on the F84, lockup from start-up no problem.

I then decided to come into the more recent world and laid hands on the F627/8. Two weeks later I found the reason that it wouldn't work; it turns out that the implementation of the XOR instruction is different between F84 and F628, and my use of the Carry bit after the XOR was not admissible, even though the code tested OK using MPSim. Had I copied your routine I would not have had a problem as you don't bother with the carry bit.!!! But, that is the trouble with going your own way !!!!!"

The asm file for Chas's code is provided to the right. Like Francis, Chas declares areas of  memory for the shift register avoiding a huge "copy and paste" exercise.



G3DXZ Version




My thanks to Peter Lawton who put forward the original idea of using a PIC as the basis for a Fast Huff Puff Stabiliser and who also conducted all of the independent testing of the designs on his trusty KW2000A. How's that for an interesting combination of technologies? As Peter put it, "I now must have the most stable KW2000A in the word." OK, I know. Having made that bold statement, someone will now just have to turn up with a Rubidium or Caesium referenced version...   


Ron Taylor G4GXO

Cumbria Designs



"It's a KW2000A Jim, but not as we know it..."

C-1 Controller Source Code

The C-1 Controller was designed as the Tx/Rx sequencer for the T-1 SSB/CW Sub System. In addition to providing full break in Tx/Rx functionality, the C-1 also provides hang AGC, variable break-in delay and a convenient control interface for all of the T-1 functions. We've decided to put the source code into the public domain to support long term maintenance of existing T-1s and to give users the possibility of customising the software to suit their specific T-1 application. This is the first version of the C-1 software  and whilst it is not particularly tidy it works well and is very well commented which should be easy to understand for those familiar with MPASM. To use the code you will need to compile it using MPLAB (MPASM) which is available as a free download on the Microchip website. The resulting Hex file is loaded into the target processor using a PIC programmer of which there are numerous versions available as kits or ready built on the internet.


At the heart of the program is a "sequencer" routine which controls up to 16 output lines. Pre-defined bit sequences are applied to the output lines to control the T-1 Tx/Rx circuitry in the right order or sequence, during Tx to Rx and Rx to Tx transitions. The sequences are hard coded into the defintions section of the program, descriptions of each control are given in the code. A sequencing delay is applied between each sequence code to allow the operation to be completed within the T-1. Normal operating controls, which also operate on many of the same controls that are driven by the sequencer, are factored into the output lines using software logic commands. Analogue interfaces are used to monitor the audio for hang AGC operation and determine the settings of the Hang AGC and Break In Delay controls.

If you produce an improved version that you would like us to post here please contact us at

C-1 Controller v1.0

Ron Taylor G4GXO

Cumbria Designs

DFT Tone Detector for the 16F628A

The Discrete Fourier Transform (DFT) is a technique commonly used to detect the presence of a signal within a spectrum. The DFT operates by multiplying samples of the input spectrum with corresponding instantaneous sine and cosine values at the frequency to be detected. The results of each multiplication are summed as Real and Imaginary magnitudes ( I and Q) from which the magnitude of the polar form of the resultant vector can be computed. When a signal is present at or near the frequency of the DFT's sine and cosine "carriers" the summed I and Q counts will be high, where there is no signal the random effects of noise and any present non synchronous signals will result in a low count. By setting a threshold level against which to compare the I and Q results signal detection is possible. The process "looks" similar to the signal flow in a direct conversion phasing receiver.

Are you saying that the 16F628A is a DSP?

The 16F series of PICs are certainly not DSPs! Whilst many 16F PICS have A to Ds they are not fast enough nor is there sufficient processing time available to perform DFT calculations on analogue signals at audio frequencies. Hence we need to make a compromise, and in this instance a rather surprising one. Instead of sampling and operating on the amplitudes of analogue signals, this approach uses square waves. The input signal is squared using one of the 16F628's comparators, the internal sine and cosine references are replaced with quadrature square wave signals. In this implementation the detection frequency is set at 800Hz and the input signal is sampled at 16 times this frequency. The rest of the processing follows the DFT process with the multiplication be performed by XOR functions and the summing processes by counters.

Key Variables

Apart from setting the detection frequency there are two key variables that affect the tone detection characteristics. The first is the Block Size. This is the number of results that are summed in the I and Q counters. the greater the number the longer the detection time, the narrower the detection bandwidth and the greater the immunity against noise and unwanted signal detection. Fewer results produce a wider detection bandwidth and increase susceptibility to noise and close in unwanted signals. The second key variable is Detection Threshold. This is closely related to Block Size and behaves in a similar way. Increasing the threshold reduces noise detection and narrows the detection bandwidth BUT requires a better signal to noise ratio for wanted signal detection - which can be realised through increased Block Size. Reducing the threshold level reduces noise immunity and widens the detection bandwidth. Some experimentation with these variables may be required for your specific application.


The audio input is applied to pin RA0 via a decoupling capacitor (100nF is fine). The reference voltage is applied to RA3 and is set at half rail by a 10K-10K divider between Vcc and Vss. A third 10K resistor is connected between RA0 and RA3 to hold RA0 at half rail potential to prevent it from floating. The detector output is an LED connected to ground via a 470R from RB0. The audio input level need only be a few tens of mV from a suitable source.

16F628A Tone Decoder.asm Note some of the formatting (e.g. waveform diagrams) may not look right in a standard file viewer. View and compile under MPLAB. This version corrects a flag error spotted by Francis Dupont and offers a significant improvement in performance.

16F628A Tone Decoder.hex  hex file with settings as per above source code.

Ron Taylor G4GXO

Cumbria Designs

RAMU the Remote Aerial Matching Unit

RAMU was conceived by Ian Keyser G3ROO as a system for matching aerials to their transmission lines at their feed points. The design appears in issue number 132 of the GQRP club's magazine SPRAT.  RAMU comprises of two parts, a control unit and a remote "head unit" at the aerial. The control unit provides the operator with two rotary encoders, an LCD display to show settings and switches to control ancillary functions. The RAMU controls are scanned by a 16F877A processor and any changes are interpreted to produce a serial data word that is transmitted over cable to the remote head unit. The head unit decodes the received serial data to drive sets of relay banks which provide incremental changes in L and C. The rotary encoders emulate the controls on a conventional aerial matching unit in that by turning them they change the settings of the corresponding L and C banks at the remote head unit. The resultant L and C values are displayed on the control unit's LCD.


This implementation of RAMU provides three logical channels within the single serial data stream, one for L, one for C and a control channel for operating ancillary relays etc. Both of the L and C channels support a range of 1000 steps and share a programmable "tuning law" to greatly speed up the tuning process. The law operates by varying the step size, increasing it at high values, reducing it at low values. The tuning law and other functions are configured in  "set up mode", the settings are saved to the 16F877A's internal EEPROM and recalled whenever RAMU is switched on. The design is highly flexible allowing several head units to be controlled from a single controller, alternatively multiple L and C configurations could also be controlled at a single head unit. There is considerable scope for further development to include band memories, (perhaps automatically selected from frequency measurement) and full automatic operation in conjunction with a VSWR sensor at the control unit. This hardware version employs a simple serial data interface at TTL levels and has been operated successfully over 150 feet (about 45m) of low cost LAN cable. The maximum potential range of this interface has not been determined but if necessary line drivers and a lower data rate could be employed to allow operation over considerable distances.

Future Development

Further development is encouraged. Should you produce any enhancements we will be pleased to post them here. Contact us at

RAMU v1a.asm RAMU source code

RAMU v1a.hex RAMU hex file

RAMU v1 schematic

Ron Taylor G4GXO and Ian Keyser G3ROO

The Digi-Pot - An antidote to expensive multi-turn potentiometers 

This project was born out of a discussion on the G-QRP club email reflector, lamenting the high price of new multi-turn potentiometers for tuning varactor controlled VFOs. The article appeared in SPRAT 139 (Summer 2009) and describes using a small 8 pin PIC12F683 processor as a variable voltage source for tuning applications. The tuning voltage is controlled by low cost mechanical encoder of the type increasingly being used in automotive audio applications. The encoder drives a software counter in the PIC which in turn sets the duty cycle of a PWM output signal generated by the PIC's internal PWM module. A simple RC low pass filter averages the PWM output to produce a DC voltage which  is applied to the VFO tuning varactor. By rotating the encoder the count increases or decreases depending upon direction. This in turn changes the DC voltage and hence the VFO frequency. A push switch on the encoder is used to instruct the PIC to toggle between two tuning rates achieved by toggling between two pre-defined step sizes that are used to increment or decrement the software counter.


The PWM module has a resolution of 1024 bits offering a tuning range of 0v to 5v (Vcc) in approximately 5mV steps. For wide tuning ranges this resolution might not be adequate and so a feature is included to dither the duty cycle by 1 bit on alternate steps. This dither averages to an intermediate mid point voltage voltage between the 5mV steps. The downside of the this technique is a half rate component in the PWM output signal which, depending upon your application may require, higher order filtering or a reduction in the corner frequency of the simple single pole filter. This feature is easily removed if not required (see source code text). Best advice is to try it first with your VFO to see if the higher resolution is necessary.

Other Tweaks

The main program constants are listed as a set of "Defines" near the beginning of the source code. These set tuning range limits and step sizes. Change these to suit your particular application;

#DEFINE LIMIT_L 0xFB ; 12 bit tuning word upper limit (with bit 2 clear to prevent dither and allowing for double count on encoder edges)

#DEFINE FINE_TUNE 0x01 ; Fine tuning step size, default is single step (0x01)
#DEFINE COARSE_TUNE 0x0A ; Coarse tuning step size, default is 10 (0x0A)

If you develop this code to include extra features or improved performance send me a copy together with a description of what changes you've made and I will post it here.

Digi Pot v1a.asm  source code

Digi Pot v1a.hex   hex file

Digi Pot schematic

Ron Taylor G4GXO

Digital AGC - A Full Wave AF derived AGC System in a PIC12F683

This design was originally conceived as an “add-on” for the Eden SSB IF system but is easily adapted for other receivers. The version described here is based on the 8 pin PIC12F683 although the software is easily adapted for any other PIC having an internal clock, analogue to digital converter (A/D) and Pulse Width Modulation (PWM) module.


Fig.1 illustrates the principal functional elements of the digital AGC system.The internal A/D samples the incoming audio to determine its amplitude either side of a centre rail bias point. A full wave detection process operates on the samples to produce a numerical AGC value which is used to set the duty cycle of a PWM waveform. The AGC voltage is generated by low pass filtering the PWM output with a simple RC filter. (This technique is identical to that described in the “Digi-Pot” article in SPRAT 139). To economise on parts and free up I/O pins, the PIC operates on its internal 8MHz clock giving an instruction time of 0.5uSec.


Audio from the receiver AF pre-amp is AC coupled to a resistive divider on the A/D input that sets a DC bias of 2.5V (mid +5V rail). The AF input is sampled by the A/D, the 10 bit result giving a resolution of about 5mV. For convenience a sampling rate of 128uSec is used (256x0.5uSec). Whilst arguably on the Nyquist limit for SSB audio, this rate has proved to be satisfactory. A simple analysis of the highest order bit of the A/D result determines whether the input is greater or less than 2.5V. The lower 8 bits of the A/D result are used to define the sample amplitude. This limits the measurable range to 2.5V+/-1.28V (2.56V p-p). Any voltage sample above the 2.5V bias point is treated as a positive value and any sample below as a negative value. As the A/D measures from “ground up”, the 8 bit values of voltages below 2.5V are complemented to obtain their difference (i.e. amplitude) from centre rail. Thus, our AF input is converted to unsigned 8 bit values representing amplitude; in effect numerical full wave detection. Audio limiting of the input signal is required to prevent it from exceeding the 2.56V peak to peak limit. In the Eden IF system limiting is achieved by two back to back diodes across the feedback resistor in the AF pre-amp.

Each new amplitude result is compared with the “threshold”; an 8 bit value representing the input voltage in 5mV steps, (5V/1024) above which AGC action is required to take place. Every time the input exceeds the threshold the “Attack” branch increases the 8 bit AGC value, every time the input is below the threshold the “Decay” branch decreases the AGC. The attack rate is set by amplitude rate of change, the two decay rates (Fast and Slow) are linear and are selected by a control pin state. The AGC byte range is 0 to 255 (0x00..0xFF) giving 256 possible values. For a typical 80dB AGC range this offers an average 80/256 = 0.3dB resolution, unnecessarily high for linear gain control IF amplifiers, but useful for “ironing out” the curves and kinks of the non linear AGC responses typical of simpler IF amplifiers.

AGC Voltage Generator

The 8 bit AGC value is converted to a voltage by PWM. The PIC’s internal PWM module is configured to run in 8 bit mode producing a continuous output at approximately 31kHz. The AGC byte sets the duty cycle of the PWM output to give 256 possible pulse widths. After low pass filtering by R4 and C5, the PWM waveform is averaged to a variable DC voltage ranging from 0V to +5V in approximately 20mV steps, (5/256V).

Buffer Amplifier

The filtered output is amplified by a rail to rail (or capable of near 0V output) Op Amp configured as a DC amplifier with a voltage gain of 2. This doubles the AGC range from the filtered output of 0V..5V to 0V..10V and increases the step resolution of about 40mV, suitable for driving the gain control input of a typical Cascode IF stage. Other output ranges may be set by adjusting the gain of the buffer stage. With most IF amplifier designs, the buffer amplifier will have plenty of spare current capacity to also drive an S-Meter circuit.


The remaining free pin count of the PIC12F683 provides 4 inputs of which two are used for controls and two are available for future development. Internal pull up resistors hold the inputs in a high control state, grounding a pin activates the low control state. Input GP0 (pin 7) sets the AGC Recovery Speed; high=fast, low=slow. Input GP1 (pin 6) sets AGC Direction; high=negative going, low=positive going.


The schematic of the AGC system published in SPRAT is shown below. As this is digital circuitry, good decoupling practice should be employed on the supply and if necessary signal and control lines, to prevent noise from entering your receiver. The prototype is installed in an MDS -136dBm 70MHz SSB transceiver based upon the Eden IF system, with no impact upon performance. Within the Eden IF, the AF input is taken from the output of IC4 the AF pre-amplifier. The AGC voltage is applied to IF Amplifier gain control input at R15. If desired manual IF gain could be retained with switching to over ride the AGC.


Please read the conditions of use at the beginning of the program listing. To compile or edit the program you will require a copy of MPLAB available free from the Microchip website; www.microchip.com.



Future Development

A considerable improvement in execution time could be realised at the expense of a couple of I/O pins, by clocking the PIC with a crystal at its 20MHz limit. A better option might be to use a higher end device, such as the 18 pin PIC18F1330, capable of 40MHz clocking with a 10MHz crystal and its internal clock multiplier, or 32MHz on its internal oscillator. Additional benefits include a useful extended instruction set, a faster A/D and higher PWM frequency offering improved suppression with simple filtering. The extra I/O pins offer plenty of scope for further enhancements such as a bar graph S-Meter and Tx/Rx sequencing, (ideas proposed by Eden Constructor Martin Rigby, G4FUI).

A GPS Disciplined 10MHz Oscillator for the Jupiter GPS Module

These notes describe a simple circuit that locks a 10MHz VCXO to the 10kHz reference output of the a Jupiter GPS receiver. This excellent high quality receiver module offers 1pps and 10kHz outputs but sadly is now long discontinued. They still appear on the second hand market, if you find one at a reasonable price buy it!


A PIC12F683 is used to divide the output of a 10MHz VCXO down to 2.5kHz and compare the phase with a 2.5kHz source derived from the Jupiter's 10kHz reference output. The action of the software is to adjust the oscillator such that it's phase and hence frequency is locked to the 10kHz Jupiter output. The phase comparator is the XOR instruction which depending upon the phase relationship of the two signals produces a 1 or 0 output on pin GP0. The phase comparator output is filtered by a long time constant circuit ( R8, C6, C8) to produce the control voltage for varying the frequency of the 10MHz VCXO. A 2N7000 serves as a power on reset switch which briefly grounds C6 and C8 to ensure that they are discharged before charging via R5 to "centre rail" the control voltage. The software incoporates a lock detector which drivess GP4 high once the frequency has stabilised.  A 74HC14 Hex invertor is used to provide signal buffering of the VCXO output. Four of the gates are paralled to form an output amplifier to increase the 10MHz output power into low impedance (~50 Ohms) loads.



Throughout the program timing is critical, the instruction cycle count is giving against each line in the code. If you make any changes be sure to check that the cumulative instruction counts are maintained or correct ioperation will not be possible.